图像缩放的研究与FPGA设计

Research and FPGA Design of Image Scaling

针对图像缩放的不同要求,提出一种分步插值图像缩放器结构。对行列在空间上分开,在时间上同步,在开始的K(选择不同的算法K值不同)行行列串行处理,先进行行缩放,再用新生成的像素点进行列操作,K行处理完后,行列并行处理。这种结构使得图像缩放时并行度得到提升,由于行列分开处理使得对于不同要求的场合行列可以采用相同或不同的算法以达到特定的要求。实验表明,该分步式插值电路架构既节省了资源、降低了开销,又提高了图像质量。

Due to various request for image scaling,present a hardware design for an image scalar. The scalar allows fractional step interpolation. It is partitioned for two-stage processing with the fast stage realizing horizontal scaling and the second stage realizing vertical scaling. Each stage in itself is a hardware pipeline. Horizontal scaling starts first. When sufficient interpolated rows are generated, vertical scaling will start and run in parallel with horizontal scaling. Both stages may use the same type of arithmetic components for interpolation although their control circuitry may be different. Experimental results indicate that this design is efficient.