JPEG2000全并行位平面编码器的VLSI设计验证

Design and verification of the parallel architecture of the bit plane coder in JPEG2000

研究了JPEG2000位平面编码器的算法和全并行电路结构.以单列样本点作为数据单元,分析了通道编码过程中数据的关联性.只需缓存前一列样本点的显著性状态信息,并读取当前列和后续2列的原始数据,便可在一个编码窗口内完成当前列的通道和位平面并行编码;每次仅需读入一列新的数据,即可实现编码循环.据此设计了三级流水线的全并行电路结构,仅需259个周期就可处理完32×32的小波子带,同时保持了较低的硬件开销.FPGA综合结果表明,系统时钟可以综合到76.355 MHz,达到301.9Mcoefficient/sec的处理能力,可满足现有图像实时处理要求.

The algorithm and parallel architecture of the bit plane coder（BPC） in joint photographic experts group 2000（JPEG2000） is studied.The data dependence in the coding passes is analyzed with a column regarded as the basic data unit.It＇s discovered that when the significance states of a former column are cached,and the original coefficients of the current column and the next two columns are ready,the parallel coding in one coding window between passes and bit planes is possible.After that,the loop-coding can be realized with a new column read in each time.Based on this conclusion,the parallel architecture with a 3 stages pipeline is designed,which can process 32×32 wavelet sub-band within 259 cycles and keep a low hardware cost.The synthesis results on FPGA（field programmable gate array） show that the system frequency can reach 76.355 MHz,and the throughput is 301.9Mcoefficient/sec.The real-time image-process can be satisfied.