逐次逼近ADC无源器件的匹配性与高层次模型

Mismatch analysis and high-level modeling of passive components in successive approximation A/D converters

对逐次逼近A/D转换器的无源器件匹配性进行了研究.基于理论分析,明确了电荷再分配结构、电压等比例缩放结构以及混合结构等几种典型逐次逼近A/D转换器对无源器件网络匹配性的具体要求,并利用Matlab工具,通过建立逐次逼近A/D转换器无源器件匹配性高层次模型对理论分析结果进行了验证.在此基础上提出了一种基于单位电容缩放的新型电荷再分配结构,在不提高无源器件匹配性要求的前提下,利用单位电容取代原有缩放电容并增加一定的时序控制,有效地解决了传统电容缩放结构中缩放电容工艺实现困难以及对寄生电容敏感的问题,适合片上系统的嵌入式应用.

The paper focuses on the research on the mismatch of the passive components in the SAR（Successive Approximation Register） ADC（Analog-to-Digital Converter）.Based on the charge redistribution,voltage division and hybrid SAR ADC architectures,the matching requirements of their internal passive component networks are explored with theoretical derivation and verified by high-level modeling using Matlab.Furthermore,without adding any matching requirement of the internal passive components,a novel charge redistribution approach based on the unit scalable capacitor is proposed.With the unit capacitor replacing the non-integral scalable capacitor and by adding several additional logic control signals,this new approach is easier to realize in process than the traditional approach and is very suitable for embedded SoC applications.