自适应均衡器的FPGA实现

Implementation of Adaptive Equalizer with FPGA

在无线通信系统中,由于多径效应的干扰导致信号在传输过程中不可避免地产生码间干扰,因此必须在接收端增加均衡器,以消除码间干扰,提高传输质量。该自适应均衡器设计以FPGA为设计平台,使用自上而下的模块化的设计方法,利用Stratix II系列EP1C20F324C6芯片,采用横向滤波器结构,设计并行结构的8阶复数滤波器。最后在QuartusII中进行仿真与综合,结果显示I、Q两路误差信号趋于零,从而实现自适应均衡,降低误码率。

In wireless communication system, because of muhipath effect, intersymbol interference （ISI） is inescapable during the data transfer. In order to eliminate ISI, equalizer has to be used in the receiver. This paper designs a 8-taps complex filter which is implemented on the Stratix Ⅱ family EP1 C20F324C6 chip with transversal filter structure and parallel computing architecture on the FPGA hardware platform based on top-down design methodology. Last, the result of simulation shows that it realizes adaptive equalizer and reduces the error rate when I, Q error signal are close to zero under the Quartus Ⅱenvironment.