层次化互连结构的EVMPSoC设计与实现

Design and Implementation of Embedded Visual Media Process SoC with Hierarchy on-Chip Bus Architecture

为满足计算密集且数据带宽大的混合多媒体应用在嵌入式系统中的实现需求,介绍了一款采用层次化互连结构的异构多核嵌入式可视媒体处理系统芯片(EVMPSoC)的设计与实现方法。该SoC芯片由一个32位嵌入式RSIC主处理器EPStar 3和两个应用定制指令集的SIMD协处理器核组成,采用层次化高低速总线和多通道双位宽并行访存结构进行互连,以满足混合多媒体处理应用的通信需求。该芯片在SMIC 0.13μm LVT CMOS工艺下一次流片成功,采用Amkor PBGA400进行封装。芯片实测结果表明,芯片的运行峰值频率为416 MHz,功能正确,效率高,具有很高的可用性。

In order to meet the high demand of computation intensive and band-width exhausting media applications for embedded system, a heterogeneous multi-core embedded visual media processor, named EVMPSoC, is proposed. The chip consists of a main processor called EPStar3, which is a 32 bit RISC embedded processor, and two SIMD coprocessor, which are designed by application-specific instruction set. According to the communication characteristics of media applications, the hierachy high/low speed bus and dual band-width parallel memory access with multi-channel are used as the on-chip bus Architecture of EVMPSoC. The chip was taped out sucessful using SMIC 0.13 um LVT CMOS technology and packaged by Amkor with PBGA 400. It runs well at peak frequency 416 MHz, and shows its high efficiency and avaliability.