期刊文献+

高速JTAG在线仿真器设计 被引量:1

Design of High Speed JTAG On-line Simulator
下载PDF
导出
摘要 给出联合测试行为组织(JTAG)边界扫描技术的概念,说明JTAG关键组件及相关的指令,介绍实际开发的通用JTAG在线仿真器。该仿真器在基于计算机并口的JTAG在线仿真器基础上进行改进,加入现场可编程门阵列,利用并口并行传输的优势,克服传统JTAG在线仿真器的速度局限性。通过自定义的通信协议,提高通信的可靠性和安全性,同时达到比传统JTAG在线仿真器更优的性能。 A concept of Joint Test Action Group(JTAG) boundary scan technology is proposed. The key components and related commands are introduced. A universal Flash simulator focusing on the engineering application is introduced. Based on the traditional JTAG on-line simulator, it adds the use of FPGA. It makes full use of the advantage of parallel transmission of parallel port and break through the speed bottleneck of the traditional JTAG on-line simulator. With self-identified communication protocol, it not only improves the reliability and security of the communication, but also realizes a higher performance than the traditional JTAG on-line simulator.
作者 余骏 党云飞
出处 《计算机工程》 CAS CSCD 北大核心 2011年第24期228-229,共2页 Computer Engineering
关键词 联合测试行为组织 边界扫描单元 现场可编程门阵列 并口 仿真器 Joint Test Action Group(JTAG) boundary scan cell Field Programmable Gate Array(FPGA) parallel port simulator
  • 相关文献

参考文献5

共引文献3

同被引文献4

  • 1IEEE Std. 1149. 1-2001, IEEE standard test access port and boundary-scan architecture [S]. 2001.
  • 2CHEN X H, ZHANG D Y,YANG H Y. Design and implementation of a single-chip ARM-based USB interface JTAG emulator [C] //Fifth IEEE Int Symp Embed Comp. Beijing, China. 2008: 272-275.
  • 3OSTENIRFF S, WUTTKE H D, SACHB E J, et al. Test pattern dependent FPGA based system architecture for JTAG tests [C] // Fifth Int Conf Syst. Menuires, Germany. 2010.. 99-104.
  • 4ICADR I, ROSTISLAV G. Internal structure of software application for controlling devices via JTAG 1149 interface [C] //East-West Design Test Symp (EWDTS). St. Petersburg, Russia. 2010.-264-266.

引证文献1

二级引证文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部