摘要
为解决传统仲裁器不能记忆请求顺序的问题,设计多路有序优先级仲裁器和有序环形仲裁器。通过先入先出(FIFO)电路来保存请求的先后顺序,将FIFO电路分别与优先级仲裁器和环形仲裁器组合,从而构成有序仲裁器。实验结果表明,该设计能简化复杂度,提高仲裁器处理请求能力,但延时和面积性能略有下降。
To improve shortcoming of traditional arbiters, this paper proposes N-way ordered arbiter, which is based on combination of First in First Out(FIFO) and priority arbiter and ring arbiter respectively. FIFO is used for savingthe request orders. It proposes a new structure of priority and a new ring arbiter. Results show that, modular design simplifies the complexity, improves the ability of arbiter to process the request, and the ability of saving the request in order reduces latency and area properties.
出处
《计算机工程》
CAS
CSCD
北大核心
2011年第24期236-238,共3页
Computer Engineering