一种数据时钟恢复电路的研究与设计

Design of a Clock and Data Recovery Circuit

提出了一种支持双数据率的数据时钟恢复电路,对电路中的鉴相器、环路滤波器、压控振荡器等进行了详细的分析研究和设计。基于0.18μm CMOS工艺,在电源电压1.8V下对电路进行仿真。仿真结果显示,电路在2.7Gb/s和1.62Gb/s随机流下的抖动峰峰值分别为14ps和12ps,功耗为80mW。测试结果显示,时钟恢复电路在2.7Gb/s和1.62Gb/s随机流下的抖动峰峰值分别为38ps和27ps。

A clock and data recovery（CDR） circuit with double data rates was proposed.Phase detector,loop filter,voltage controlled oscillator in the circuit were analyzed in detail.Based on 0.18 μm CMOS process,the circuit was simulated at 1.8 V power supply.Simulation results showed that the clock and data recovery circuit had a peak-to-peak jitter of 14 ps and 12 ps at 2.7 Gb/s and 1.62 Gb/s data rates,respectively,and it consumed 80 mW of power.Test results indicated that the clock and data recovery circuit had a peak-to-peak jitter of 38 ps and 27 ps at 2.7 Gb/s and 1.62 Gb/s data rates,respectively.