期刊文献+

JFET区注入对大功率VDMOS击穿电压和导通电阻的影响 被引量:2

Effect of Ion-Implanted JFET Region on Breakdown Voltage and On-Resistance of Power VDMOS Device
下载PDF
导出
摘要 研究了JFET区注入对大功率VDMOS器件击穿电压和导通电阻的影响,分析讨论了JFET区注入影响击穿电压的机理,并定量给出JFET区注入对导通电阻的影响。通过器件数值模拟优化JFET区注入剂量,并根据仿真结果改进器件设计,在满足击穿电压要求的前提下导通电阻降低了8%。 Effect of ion-implanted JFET region on breakdown voltage and on-resistance of power VDMOS device was investigated.Mechanism of breakdown voltage drop induced by implantation into JFET region was discussed,and effect of implantation in JFET region on on-resistance was quantitatively analyzed.By optimizing implantation dosage with TCAD and modifying device design according to simulation results,on-resistance of the device was reduced by 8%,and breakdown voltage didn't drop significantly.
出处 《微电子学》 CAS CSCD 北大核心 2011年第6期918-922,共5页 Microelectronics
基金 国家自然科学基金资助项目(60820106001)
关键词 JFET VDMOS 击穿电压 导通电阻 JFET VDMOS Breakdown voltage On-resistance
  • 相关文献

参考文献7

  • 1陈龙,沈克强.VDMOS场效应晶体管的研究与进展[J].电子器件,2006,29(1):290-295. 被引量:18
  • 2MORANCHO F, TRANDUC H, ROSSEL P. The on- resistance limits of high cell density power MOSFETs [C] // 21s' Int Conf Microelec Proceed. Nis, Yugoslavia.1997, (1): 395-398.
  • 3姜艳,陈龙,沈克强.VDMOS的导通电阻模型[J].电子器件,2008,31(2):537-541. 被引量:8
  • 4EVANS J, AMARATUNGA G. The behavior of very high current density power MOSFETs [J ]. IEEE Trans Elec Dev, 1997, 44(7): 1148-1153.
  • 5CHIEN F, LI T, LAI P, et al. High voltage power MOSFET with reduced JFET area design [C] // 2nd IEEE Int Symp Power Elee Distributed Generation Systl Hefei, China. 2010: 526-529.
  • 6NG J C W, SIN J K O, GUAN L P. A novel planar power MOSFET with laterally uniform body and ion implanted JFET region [J]. IEEE Elec Dev Lett, 2008, 29(4) : 375-377.
  • 7HAKIM H, BOLOGNESI D, DE PESTEL F. Integrated VDMOS transistor with reduced JFET effect [C] // Proc 36th Europ Sol Sta Dev Resear Conf. Montreux, Switzerland. 2006: 278-281.

二级参考文献32

  • 1张品福,张克善.VDMOS场效应管及其特点分析[J].半导体杂志,1997,22(3):39-44. 被引量:7
  • 2Syau T,Venkatraman P,Baliga B J.Comparison of Ultralow Sepcific On-Resistance UMOSFET Structures[J].IEEE Trans.Electron Devices,1994,41:800-808.
  • 3Baliga B Jayant.The Future of Power Semiconductor Device Technology[C].In:Proceedings of the IEEE,2001,89(6):822-832.
  • 4Lorenz L,Deboy G.COOLMOSTM-a New Milestone in High Voltage Power MOS[C].In:Proc ISPSD,1999,:3-10.
  • 5Yeong S.K,Jerry G.Physical DMOST Modeling for High-Voltage IC CAD[J].IEEE Trans.Electron Devices,1990,37(3):797-803.
  • 6Park C.K,Lee Kwyro.Experiments and 2D-Simulations for Quasi-Saturation Effect in Power VDMOS Transistors[C].In:Proc ISPSD,1990:219-224.
  • 7Krishna S.A 55V,0.2-mΩ穋m2 Vertical Trench Power MOSFET[J].IEEE Electron Device Letters,1991,12(3):108-110.
  • 8Kim J,kim S G.High-Density Trench Gate DMOSFETs with Trench Contact Structure[J].Electronics Letters,2004,40(11).
  • 9Tsui B Y,Gan T C.A Novel Fully Self-Aligned Process for High Cell Density Trench Gate Power MOSFETs[C].Proc.ISPSD,2004:205-208.
  • 10M.A.A.in't Zandt,et al.Record Low Specific On-Resistance for Low-Voltage Trench MOSFETs[J].IEE Proc-Circuits Devices Syst.,2004,151(3):269-272.

共引文献24

同被引文献19

引证文献2

二级引证文献9

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部