DDS捷变频信号发生器中的FPGA控制电路设计

Design of the FPGA control circuit of the DDS frequency agile signal generator

选取AD9910作为频率合成模块,利用FPGA生成伪随机频率控制码,通过AD9910并口改变其频率调谐字,控制AD9910输出频率的快速跳变。利用FPGA产生脉宽、重频可控的脉冲调制波形,以脉冲调制波形提供的时钟实现伪随机码生成时序、频率跳变时序、脉冲调制时序的统一,产生在整个频段随机捷变的信号。此种方法时序控制简单,可以将频率跳变的时间控制在500ns以内,跳变速度远高于利用DDS串口实现跳变的速度,输出脉间随机捷变信号分辨率高,系统性能稳定。

Choosing the AD9910 as a frequency synthesis module,using the pseudo-random frequency control code generated by the FPGA,can change its frequency tuning word by the AD9910 parallel port and make the AD9910 realize the fast hopping of the output frequency.Using the pulse width,pulse-repetition-rate adjustable modulation waveform generated by FPGA to provide the clock,which can achieve the unity of the pseudo-random code generation timing,frequency hopping timing and pulse modulation timing and generate the random agile signal over the entire band.This method is simple in timing control,frequency hopping can be controlled within 500 ns,the speed of hopping is much faster than that of the serial port using DDS,the output of the random frequency-agile signal between the pulse interval has high resolution and the system performance is stable.