基于FPGA的信道化数字接收机的研究与仿真

Research on Digitized Channelized Receiver and Its Simulation Based on FPGA

雷达电子战数字信道化接收机能够处理同时到达的多个信号并有较高的截获概率,是当前国内外研究重点。采用了一种基于多相滤波结构的宽带数字信道化接收机方法,通过信道化降低后续信号处理速度,可满足宽频段覆盖、高灵敏度、高截获概率和实时处理能力。对系统基于FPGA实现信道化数字接收机,时分复用完成算法。

Broadband radar electronic warfare channelized digital receiver have the capable of handling multiple signals arrived simultaneously and have a higher probability of intercept,which is researched as priorities in domestic and international in the current.A polyphasefilter structure based on the broadband digital channelized receiver is used,with the method of channelized to slow down the processing speed of the follow-up signal to meet the wide frequency coverage,high sensitivity,high probability of intercept and real-time processing capability.The system based on FPGA channelized digital receiver,time division multiplexing is completed algorithm.