摘要
针对数字射频存储器(DRFM)量化方式的差异、优势和不同的应用范围,介绍相位量化模数转换器(ADC)的系统架构,提出相位量化ADC主要电路模块的一种实现方案,比较了该方案与传统方式的区别,并基于0.13μm互补型金属氧化物半导体场效应晶体管(CMOS)工艺模型进行仿真,仿真结果表明该芯片可在1.2 GHz时钟速率下完成采样、量化,瞬时带宽可达250 MHz,具有+0.2 LSB的相位精度。
The paper discusses and analyzes the difference between and the advantages of the various quantization modes of digital radio frequency memory （DRFM）, and introduces the architecture of a 4-bit phase quantization ADC. An implementation scheme of the main circuit modules of phase quantization ADC is presented and compared with the traditional method. Based on 0.13 um CMOS technology, the simulation indicates that this circuit can accomplish sampling and quantization at 1.2 GHz clock rate, the IBW is 250MHz, the phase accuracy is 0. 2LSB.
出处
《无线电通信技术》
2011年第6期40-42,49,共4页
Radio Communications Technology
关键词
数字射频存储器
相位量化ADC
比较器
digital radio frequency memory
phase quantization ADC
comparator
