一种适合硬件实现的H.264/AVC宏块级码率控制算法

Facilitating Hardware Implementation MB-level Rate Control Algorithm for H.264/AVC

主要针对H.264/AVC编码器硬件实现时的特点,提出了一种适合硬件实现的高效码率控制方案。为了提高数据处理效率,硬件编码器通常采用Zigzag宏块编码顺序和宏块级流水结构,两者结合会产生复杂的数据依赖关系。在数据依赖存在的条件下,提出了利用时域和空域相关性预测帧级和宏块级平均绝对误差(MAD),提高预测精度获取合适的量化参数。实验结果显示与G012算法相比,该算法提高了MAD预测精度,平均PSNR提高了0.12 dB,解决了硬件实现时的数据依赖问题。

This paper mainly aims at the characteristics of H. 264/AVC hardware encoder architecture, and an efficient rate control algorithm facilita- ting hardware implementation is proposed. In order to imp：rove the efficiency of data processing, hardware encoder usually adopts Zigzag macroblock （MB） encoding sequence and MB pipe-line structure, but the combination of them results in complex data dependencies. In the condition, the temporal and spatial correlation between predicted frame level and MB-level mean absolute error （MAD） is used, to improve the prediction accuracy and obtain suitable quantization parameters. Compared with G012 algorithm, the experimental results show that the proposed algorithm improves the prediction accu- racy of MAD, achieves an average PSNR gain of 0. 12 dB and solves the problem of data dependencies.