基于FPGA的数字乘法器性能比较

Performance Comparisons for FPGA-Based Digital Multipliers

详细描述了四种基本的FPGA数字乘法器设计方法即阵列法、查找表法、移位相加法、Booth法的原理和实现过程。以4×4和16×16数字乘法器的设计为例,通过在AlteraFPGA芯片上的仿真与综合,给出了这四种数字乘法器的运算速度和占用逻辑资源情况。结果表明随着位宽的变化,各方法的相对效果会有变化,对于具有较宽数据位的乘法器来说,使用Booth方法有明显的优势,而移位相加法可明显的节省片上硬件资源。

The principles and realizing processes of four kinds of FPGA digital multipliers which are named array, look-up table, shift-add and Booth are described in detail. By simulation and synthesizing of the four kinds of FPGA digital multipliers in Altera FPGA chip, the performances in speed and resources consumption are also presented with 4×4 and 16×16 digital multipliers as examples. The results show the Booth multiplier has evident advantages when Multiplier has larger data width while the shift-add multiplier can economize resources in chip.