IC封装中互连线信号完整性的研究

Research of Signal Integrity of Interconnection in IC Packaging

随着电子芯片向着高密度、高频率和小体积化方向发展,IC封装的结构尺寸及其互连线系统在信号完整性、损耗等多方面影响着整个电路系统的可靠性。因此,对IC封装及其互连线电特性的分析显得尤为重要。文章以四列直插芯片封装外壳模型为设计实例,利用Ansoft Q3D软件提取了该封装模型的寄生电阻、电容和电感(RCL),并结合Multisim软件对封装互连线上的信号完整性进行了简单的Ⅱ端口等效电路分析。从中认识到,随着频率的升高,由于寄生参数特别是寄生电感的存在,IC信号的性能会随之降低。IC封装设计者应使用协同设计的方法和理念,在有效提高封装电特性的同时降低封装成本及研发周期。

With the IC chip is moving toward to high-density, high frequency and small size, the structure of the IC package and the interconnection has a great influence on the system reliability in the aspect of signal integrity and loss. So, we have to pay attention to the analysis of the electrical characteristics of IC package and the interconnection. A real example of four split in line IC package was used to extract the parasitic of RLC with the Ansoft Q3D software. At the same time, the signal integrity of the intercormection has been analyzed by a two-port circuit model with the Multisim software. Then the conclusion can be obtained that the performance of IC signal will drop bec, ause of the parasitic in the package as frequency goes higher. The package designer should use the idea and method of the co-design to improve the electrical characteristics of packaging meanwhile reducing the packaging costs and shortening the research cycle effectively.