低成本可调FFT处理器的超大规模集成电路设计

Low Cost VLSI Design of a Flexible FFT Processor

文章提出了一种以基-22/23为基础的流水线结构,用以实现低成本、超大规模集成电路(VLSI)的快速傅里叶变换(FFT)处理器设计。该处理器在减少普通复数乘法器级数的同时,通过单路延时反馈(SDF)存取方式,以最少的存储字来获得FFT结果。对于数据通路,我们采用了混合浮点的数据缩放方式,在保证信噪比的同时,降低了数据长度和RAM容量的需求。

In this paper, a radix-22/23 based pipeline structure is presented, in order to implement a low-cost VLSI fast Fourier transform （FFT） processor. As well as reducing the steps of normal complex multiplications, it minimizes the memory words to get the FFT results with the single-path delay feedback （SDF） memory access method. As for the data-path in the pipeline FFT processor, the hybrid floating point data-scaling scheme is adopted to achieve enough signal-to-quantization-noise ratio with minimum data width and RAM requirements.