一种带有插值滤波器的8位650MHz采样速率数字模拟转换器

An 8 bit 650 MHz Current-steering CMOS D/A Converter with Interpolation Filter

针对OFDM-UWB标准超宽带收发系统中数模转换器(DAC)的要求,设计了一款8位650MHz采样速率电流驱动型数模转换器(Current-steering DAC)。为了提高静态性能,本设计通过蒙特卡洛分析确定电流源最佳尺寸并采用双中心版图技术;为了提高动态性能,文中采用共源共栅电流源结构,对开关电压降摆幅处理并在数字输入端前加入插值滤波器。测试结果表明,DAC的积分非线性(INL)和差分非线性(DNL)分别为0.3LSB和0.41LSB,650MHz转换速率下带内奈奎斯特无杂散动态范围(SFDR)为41dB。整体面积为1.8cm×1.3cm,其中DAC面积为0.8cm×0.8cm。

To be applied in the MB-OFDM UWB System, an 8 bit 1-G samples/s currentsteering DAC is designed in this paper. To improve the static performanee, the eurrent source transistor size is decided by the Monte Carlo analysis and the double centroid layout technique is used to achieve a high frequency performance, the eascode current source is used, the voltage swing of the switch transistor is reduced and the interpolation filter is added in the front digital part. The measured integral nonlinearity （INL） and differential nonlinearity （DNL） are 0.3 LSB and 0.41 LSB, respectively, and the measured Nyquit spurious free dynamie range （SFDR） is 41 dB for signals in band width at 650 MS/s clock. The whole area is 1.8 cm×1.3 cm and the DAC＇s area is 0.8 cm×0.8 cm.