流水线结构RS(255,223)译码器的VLSI设计

A VLSI DESIGN OF PIPELINE RS(255,223) DECODER

ＲＳ码已经广泛应用于通信系统、计算机系统、存储介质、网络和数字电视中，以提高数据的可靠性；ＲＳ（２５５，２２３）码是美国航空航天局（ＮＡＳＡ）和欧洲空间站（ＥＳＡ）在深空卫星通信系统中所采用的标准外码．文中用Ｔｏｐ－ｄｏｗ ｎ 设计方法完成了采用频域译码算法的ＲＳ（２５５，２２３）译码器的ＶＬＳＩ设计，提出了一个ＧＦ（２５６）上串行计算的流水线结构的２５５点ＩＦＦＴ，该结构的ＩＦＦＴ与译码器的其它模块可形成完美的流水线，减少了面积，提高了通过率．设计的规模约２０万门，总的时延为７８０ 个时钟周期，工作频率为２０ＭＨｚ时，译码器的通过为１６０ Ｍｂｐｓ．

RS code is widely used in communication systems, computer systems, storage media, network, and digital television to enhance data reliability; RS(255,223) code is the standard outer code in the concatenated code system of the deep space satellite communication adopted by NASA and ESA. A VLSI design of pipeline RS(255,223) decoder in frequency domain is presented and a pipeline IFFT with 255 points in GF(256) is proposed in this paper. This design is modeled in VHDL; the verified gate level netlist is obtained after synthesizing the VHDL model. The complexity of RS(255,223) decoder is about 200,000 gates, the total latency is 780 cycles, and the throughput is 160Mbps under 20MHz. Comparing with similar designs, this design has smaller latency, moderate area, and high throughput rate.