基于全数字锁相环的基波频率测量算法

Fundamental frequency estimation algorithm based on an all digital phase locked loop

本文提出了一种用于电能计量芯片的基波频率测量算法。其创新点是从系统设计出发,把基波频率测量与电能计量中过采样ADC的梳状积分级联抽取滤波(以下简称CIC)过程相结合,利用CIC、正交去调鉴频器、PI调节器和基波频率-CIC抽取率转换器共同构成一个全数字锁相环(以下简称ADPLL)。该锁相环可以有效地抑制输入信号中的直流、谐波和噪声,并且其硬件实现所需的计算单元和存储单元都很少,非常适合芯片化的产品应用开发。

In this paper a novel fundamental frequency estimation algorithm used for energy metering cnlp is proposed.The main innovation point of the algorithm is to combine frequency estimation with the decimation process of cascaded comb integrator （CIC） filter of over sampling ADC, using a quadrature demodulation module, a PI regulator, a frequency to CIC down sample rate converter to form an all digital phase locked loop （ADPLL）. The ADPLL can suppress the noise, direct current and harmonics of the input signal. Moreover, the realization cost of this algorithm is relatively low, making it very suitable for chip design implementation.