一种OTP存储器高速读出机制的设计

Design of a High Speed Read-Out Mechanism for OTP Memory

本文设计了一种用于OTP存储器的高速读出机制.该读出机制由内部电路产生读控制时序,采用地址变化探测电路、脉冲宽度调整及控制信号产生电路、采样与锁存电路来实现读取操作.其具有电路结构简单,读出速度快,读出准确,抗噪声、抗干扰能力强,功耗低的特点.仿真结果表明整个读取周期仅为24ns,数据口的读出信号稳定准确,不会产生读取误操作.

A high speed read-out mechanism for OTP memory is proposed.The mechanism produces read control timing by its internal circuits.Address transition detection（ATD）,pulse width modulation,control signal generation,sampling and latch modules are adopted in the proposed circuit,achieving good performance in simplicity,rapidity,accuracy,tolerance of noise and interference and low power consumption.Simulation shows that the entire reading period is merely 24ns and the read-out process can be completed stably and accurately without mistakes.