在Altera的FPGA中实现高速Link口的时序约束方法

Constraining Multiple High-Speed Link Ports in Altera's FPGA

在FPGA内部布线资源有限的情况下,将多路TS201 Link口的接口逻辑约束在FPGA固定的区域内并使它达到较高的传输速度,是一件很困难的事情。在Altera的FPGA开发中,正确地利用SDC(synop-sys design constraints)时序约束方法和TimeQuest时序分析器可以使这件事情变得容易。详细地讲述了在FPGA中对多路全双工Link口的接口逻辑进行时序约束的方法,并使Link口的传输速度达到300 MB/s。

It is difficult to realize multiple TS201 Link port logic in certain area of an FPGA and make sure that each Link port logic could operate at a relatively high speed.Accurately using SDC timing constraints and TimeQuest timing Analyser could make it easier.A concrete timing constraint method was presented to realize multiple full-duplex Link port logic at a speed of 300 MB/s.