Cache漏流功耗的自适应优化:动态容量调整

Dynamic Resizing: Adaptive Optimization for Cache Leakage Power

当集成电路制造工艺水平发展到超深亚微米阶段,漏流功耗所占的比例越来越大,成为微处理器功耗的重要来源。漏流功耗同电压、漏电流和晶体管数量等因素密切相关。Cache是微处理器中面积较大的部件,对其漏流功耗进行优化是微处理器低功耗设计的首要任务。除了采取工艺上的改进措施外,cache漏流功耗可以通过把握或改变cache的工作状态来进行体系结构级的自适应优化。提出了基于"逻辑路"的cache动态容量调整策略。模拟结果显示,在相联度较高的cache中,基于"逻辑路"的动态容量调整策略可以在几乎不影响性能的前提下,将cache的漏流功耗降低约76.6%。

The power leakage covers more and more of the consumption of power, especially when the production of highly integrated circuit has reached the level of very deep submicron, thus it becomes the main source of the power leakage of the microprocessor. Power leakage is closely related to voltage, leakage current and the amount of transistors. Cache is the sizable fraction of the total microprocessor, and its leakage power optimization must be firstly considered in low power microprocessor design. Besides process improvement, the leakage power of caches can be adaptively reduced by monitoring and controlling its operating states at architectural level. In light of this idea, a dynamic resizing policy based on cache replacement algorithm was proposed. The cache was dynamically resized on so-called logical way granularity according to cache operating states. Simulation results show that dynamic resizing policy can reduce cache leakage power by 76. 6% without obviously performance drop, especially for high associative caches.