摘要
以IEEE 754标准为基础,完成了双精度浮点除法器的设计。整个设计包括预处理、指数减、尾数除、规格化、舍入判断、溢出判断和异常处理六部分。在尾数除部分用了SRT基4算法和改进的全并行基4、基8、基16和基256这5种不同的除法算法来实现。并分析了仿真和逻辑综合的结果,它们各自有不同的优点,可以适用不同的场合。如果综合考虑时钟周期数、时延、面积等方面的因素,全并行基8和基16算法是比较理想的选择。
Based on the IEEE754 standard, a double precision floating point division is designed. The whole design include six parts, which are preprocess, exp_sub, fra_div, format_rounding, overflowing and exception. The fra_div is implemented by five different arithmetic, which include SRT radix -4, improved parallel radix - 4, radix - 8, radix - 16 and radix - 256. This paper also analyses the result of the simulation and logic synthesis, and find out they can be used on different places because of their virtue. If considering factors of clock, delay and area,parallel radix- 8 and radix- 16 arithmetic is perfect choice.
出处
《微处理机》
2011年第6期1-5,共5页
Microprocessors
关键词
除法器
算法
SRT基4
并行
Division
Arithmetic
SRT radix - 4
Parallel
