基于上下文预测算法的位平面解码器VLSI设计

VLSI Design for Bit Plane Decoder Based on Context Prediction Algorithm

位平面解码器作为JPEG2000解码系统中算法复杂、运算量最大的组件,限制了解码器的工作效率,为此,以下提出了一种上下文预测算法,并将该算法与基于组的像素点跳跃算法混合使用,实现了数据处理的流水线操作,提高了位平面解码器的工作速度。并采用Verilog HDL硬件描述语言进行了RTL级描述,经过功能仿真和DC综合,最高工作频率可达100MHz,内嵌到JPEG2000解码器系统中,可满足图像实时解码的要求。

As the computational intensive and complicated process module, the bit plane decoder becomes the main bottleneck for improving the speed of ]PEG2000 decoding system. In this paper, we proposed a context prediction method, and the GBPS （ Group - Based Pixel Skipping） scanning method is also used. The Decoding efficiency is improved. The whole design was described by Verilog HDL language, The highest frequency of the design is up be used for real -time image processing. to 100MHz after simulation and DC synthesis. It can