一种高效的AVS自适应环路滤波器硬件设计

Efficient Hardware Design of Self-adaptive Loop Filter Based on AVS

提出了一种高效的AVS自适应环路滤波器的结构设计。滤波器设计了5级流水线结构,通过优化滤波顺序,合理地安排片上存储空间,大大缩短了处理一个宏块的周期。提出的设计结构,处理一个宏块只需要112个周期。实验表明,使用0.18μm SMIC CMOS库,在125 MHz频率下综合,所提出的结构只需20.7千门,可以被用于AVS高清视频的实时滤波处理。

In this paper, an efficient hardware architecture proper for self-adaptive loop filter in AVS is presented. In this architecture, five stage pipeline filter core with the data storage carefully organized and novel filtering order is proposed so as to highly reduce the cycles of one macroblock. Only 112 clock cycles are needed to finish filtering a macrohlock for loop filter in AVE The experimental results show that the proposed design can achieve 125 MHz only with gate count of 20. 7 k by using 0. 18μm SMIC CMOS technology, and this design satisfies the requirement of real-time filter of high definition video.