摘要
针对传统的FIR滤波器的缺点,介绍了一种基于FPGA乘法器的FIR滤波器设计方法,该滤波器利用FPGA自带的18位乘法器MULT18×18SIO进行乘法计算,利用寄存器对相乘结果进行累加,实现了FIR滤波功能。该滤波器具有占用极少的资源、提高滤波速度和高速灵活性等优点。
For the shortcomings of the traditional FIR filter, an FPGA-based FIR filter design multiplier method is introduced. The filter can make use of the 18 bit multipliers MULT18 × 18SIO of FPGA to multiply, and take advantage of register accumulates implement to accumulate, implement the FIR filtering. The filter has advantages as taking little resource, improveing the filtering speed and high-speed flexibility and so on.
出处
《电视技术》
北大核心
2012年第3期40-42,73,共4页
Video Engineering
基金
国家自然科学基金项目(60871041)
