期刊文献+

采用字典词条衍生模式的测试数据压缩 被引量:4

Test Data Compression Using Entry Derivative Mode of Dictionary
下载PDF
导出
摘要 为了降低数字集成电路测试成本,压缩预先计算的测试集是一种有效的解决途径。该文根据索引位数远少于字典词条,以及测试数据中存在大量无关位,提出一种采用词条衍生和二级编码的字典压缩方案。该方案引入循环移位操作,确保无关位按序任意移动而不丢失,从而扩大词条衍生性能,减少非词条向量个数。另外,采用规则的两级编码可以减少码字数量和解压电路的复杂度。实验结果表明该文所提方案能够进一步提高测试数据压缩率,减少测试时间。 To lower cost of testing digital integrated circuits,compressing precomputed test set is an effective resolution way.A dictionary compression scheme using entry derivative and two-level coding is proposed based on digits of index far fewer than that of dictionary entry and enormous don't-care bits in test data.The introduced cyclic shift operation can arbitrarily shift don't-care bits in order without losing them so that derivative performances of entries are expanded and number of non-entry vectors is decreased.In addition,two-level regular coding is adopted to reduce volume of code words and complexity of decompression circuit.The experimental results show that the proposed scheme can farther heighten test data compression ratio and decrease test time.
出处 《电子与信息学报》 EI CSCD 北大核心 2012年第1期231-235,共5页 Journal of Electronics & Information Technology
基金 教育部博士点基金(200803590006) 安徽省海外高层次人才基金(2008Z014) 安徽省高校省级自然科学研究基金(KJ2010A280 KJ2010B428)资助课题
关键词 集成电路 测试数据压缩 字典压缩方案 循环移位 Integrated circuit Test data compression Dictionary compression scheme Cyclic shift
  • 相关文献

参考文献13

  • 1Touba N A. Survey of test vector compression techniques[J]. Design & Test of Computers, 2006, 23(4): 294-303.
  • 2Chandra A and Chakrabarty K. Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes[J]. IEEE Transactions on Computers, 2003, 52(8): 1076-1088.
  • 3El-Maleh A H. Test data compression for system-on-a-chip using extended frequency-directed run-length code[J]. IET Computers & Digital Techniques, 2008, 2(3): 155-163.
  • 4彭喜元,俞洋.基于变游程编码的测试数据压缩算法[J].电子学报,2007,35(2):197-201. 被引量:33
  • 5Kongtim P and Reungpeerakul T. Parallel LFSR reseeding for mixed-mode BIST[C]. International Conference on Electrical Engineering/Electronics Computer Telecommunications and Information Technology (ECTI- CON), Chiang Mai, Thailand, 2010: 198-202.
  • 6Kim Hong-sik and Kang Sung-ho. Increasing encoding efficiency of LFSR reseeding-based test compression[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(5): 913-917.
  • 7El-Maleh A H. An efficient test vector compression technique based on block merging[C]. Proceedings of IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, 2006: 1447-1450.
  • 8Yi M X, Liang H G, Zhang L, et al.. A novel X-ploiting strategy for improving performance of test data compression[J]. IEEE Transactions on Very Large Scale Integration ( VLS1) Systems, 2010, 18(2): 324-329.
  • 9Kavousianos X, Kalligeros E, and Nikolos D. Optimal selective Huffman coding for test-data compression[J]. IEEE Transactions on Computers, 2007, 56(8): 1146-1152.
  • 10Kavousianos X, Kalligeros E, and Nikolos D. Test data compression based on variable-to-variable Huffman encoding with codeword reusability[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(7): 1333-1338.

二级参考文献11

  • 1韩银和,李晓维,徐勇军,李华伟.应用Variable-Tail编码压缩的测试资源划分方法[J].电子学报,2004,32(8):1346-1350. 被引量:27
  • 2A Jas, J Chosh-Dastidar. Scan vector compression/de-compression using statistical coding[ A]. IEEE VLSI Test Symposium [ C] .San Diego, California, USA. Apr, 1999.114 - 121.
  • 3T Yamaguchi, M Tilgner, et al. An efficient method for compressing test data [ A ]. the IEEE International Test Conference[ C ]. Washington DC, USA, 1997.79 - 88.
  • 4A Chandra, K Chakrabarty. System-on-a-chip test-data compression and decompression architectures based on golomb codes[ J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2001,20(3) :355 - 368.
  • 5A Chandra, K Chakrabarty. Frequency-directed run length (FDR) codes with application to system-on-a-chip test data compression[ A]. IEEE. VLSI Test Symposium[C].Marina Del Rey, Califomia, USA. 2001.42 - 47.
  • 6P T Gonciari,B M Al-Hashimi. Variable-length input Huffman coding for system-on-a-chip test [ J]. IEEE. Transactions on Computer-Aided Design of Integrated Circuits and Systems,2003,22(6) :783 - 796.
  • 7A Chandra, K Chakrabarty. A unified approach to reduce SOC test data volume, scan power and testing time [ J]. IEEE Tramactions on Conputer-Aided Design of Integrated Circuits and Systems,2003,22(3) :352- 362.
  • 8J Saxenu,K Butler, L Whetsel. An analysis of power reduction techniques in scan testing[ A ]. IEEE International Test Conference[C]. Baltimore, USA, 2001.670 - 677.
  • 9R Sankaralingam, R P Oruganfi, N A Touba. Static compaction techniques to control scan vector power dissipation [ A]. IEEE VLSI Test Symposium[ C] .Montreal, Canada,2000.35 - 40,
  • 10I Hamzaoglu, J H Patel. New techniques for deterministic test pattern generation [ A ]. IEEE. VLSI Test Symposium [ C ]. Princeton, New Jersey, USA, 1998.446 - 452.

共引文献32

同被引文献40

  • 1吴国清,陈虹.一种科学数据无损压缩方法[J].计算机工程与应用,2006,42(5):172-175. 被引量:14
  • 2Touba N A.Survey of test vector compression techniques[J].Design & Test of Computers,2006,23(4): 294-303.
  • 3Chandra A and Chakrabarty K.Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes[J].IEEE Transactions on Computers,2003,52(8): 1076-1088.
  • 4Gonciari P T,AI-Hashimi B M,and Nicolici N.Variable- length input huffman coding for system-on-a-chip test[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2003,22(6): 783-789.
  • 5Kavousianous X,Kalligeros E,and Nikolos D.Optimal selective huffman coding for test-data compression[J].IEEE Transaction on Computers,2007,56(8): 1146-1152.
  • 6Sismanoglou P and Nikolos D.Input test data compression based on the reuse of parts of dictionary entries: static and dynamic approaches[J].IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems,2013,32(11): 1762-1775.
  • 7Sismanoglou P and Nikolos D.Test data compression based on reuse and bit-flipping of parts of dictionary entries[C].Proceedings of 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems,Warsaw,Poland,2014: 110-115.
  • 8Han Yin-he,Hu Yu,Li Hua-wei,et al..Ripad and energy- efficient testing for embedded cores[C].Proceedings of 13th IEEE Asian Test Symposium,Washington DC,USA,2004: 8-13.
  • 9Ruan X and Katti R.An efficient data-independent technique for compressing test vectors in systems-on-a- chip[C].Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures,Karlsruhe,Germany,2006: 153-158.
  • 10Lin Shih-ping,Lee Chunag-len,Chen Jwu-e,et al..A multilayer data copy test data compression scheme for reducing shifting-in power for multiple scan design[J].IEEE Transactions on Very Large Scale Integration(VLSI) Systems,2007,15(7): 767-776.

引证文献4

二级引证文献28

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部