期刊文献+

COTS星载双模测控应答机基带设计与实现

Design and Implementation of Dual-Mode Satellite TT&C Transponder Baseband System with COTS Components
下载PDF
导出
摘要 提出了一种星载双模测控应答机基带设计方案,采用COTS(商用现货)器件实现,能较好解决星载功率受限和空间辐射效应引起的相关问题。测控应答机主处理器由反熔丝FPGA(现场可编程门阵列)实现,可在低功耗条件下保证最基本测控需求,解调上行DPSK(差分相移键控)信号,调制下行扩频信号;协处理器受主处理器控制,由SRAM(静态存储器)FPGA来实现,对上行扩频信号进行解扩解调。测控应答机可根据星载电源功率情况和不同测控任务切换模式,具有成本低、可靠性高、使用灵活等优势。 This paper presents a design of dual-mode satellite TTC transponder baseband system implemented with commercial off-the-shelf components to provide solutions to limited onboard power and space radiation effects.The primary processor of the TTC transponder,an anti-fuse FPGA,demodulates uplink DPSK signals and modulates downlink spread spectrum signals to meet basic TTC requirements at low power consumption.The coprocessor,which is controlled by the primary processor,is an SRAM FPGA serving as a demodulator for the uplink spread spectrum signals.The TTC transponder switches its operation mode based on available power onboard and TTC tasks and it has the advantages of low cost,high reliability and flexibility.
出处 《飞行器测控学报》 2011年第6期16-20,共5页 Journal of Spacecraft TT&C Technology
基金 国家重大专项(No.2009ZX03005-002-02) 中国科学院微小卫星重点实验室开放研究基金资助课题(10004)
关键词 卫星通信 测控 应答机 软件无线电 基带设计 Satellite Communication Telemetry Tracking and Command(TT&C) Transponder Software Radio Baseband Design
  • 相关文献

参考文献11

  • 1Hodson R F, Somervill K, Williams J, et al. An Architec- ture for Reconfigurable Computing in Space[C]//Military and Aerospace Applications of Programmable Devices and Teeh nologies Conference (MAPLD), Washington DC: NASA Of- rice of Logic Design, 2005.
  • 2Nishinaga N, Takeuchi M, Suzuki R. Reconfigurable Com- munication Equipment on SmartSAT 1 [C]// Military and Aerospace Applications of Programmable Devices and Tech nologies CoMerence(MAPLD), Washington DCNASA Of {ice of Logic Design , 2004.
  • 3Toshinori K. FPGA-Based Reconfigurable On-Board Compu- ting Systems for Space Applications[D]. German Stuttgart: Institute of Space Systems University Stuttgart, 2009.
  • 4邢克飞.星载信号处理平台单粒子效应检测加固技术研究[D].长沙:国防科学技术大学,2007.
  • 5Actel Ltd. Total System Power in FPGAs[EB/OL] (2006 - 06) [ 2011 - 04]. http ://www. actel, com/documents/Under- standingFPGAPower, pdf.
  • 6Habinc S. Lessons Learned from FPGA DevelopmentsEEB/ OLd. (2002 - 04:) 1-2011 - 041. http://mieroelectronics, esa. int/asic/fpgq 001_01-0-2. pdf.
  • 7Xilinx Ltd. Virtex-6 Family Overview[EB/OL]. (2009 -09) [ 2011 - 043. http ~//www. xilinx, com/support/documenta tion/data_sheesh/dsl 50. pdf.
  • 8Padovani R. Reconfigurable Field Programmable Gate Arrays (FPGAs) for Space-present and Future[C]//Military and Aerospace Applications of Programmable Devices and Tech- nologies Conference (MAPLD), Washington DC: NASA Office of Logic Design, 2005.
  • 9Carmichael C, Chen W T. Correcting Single-event Upsets with a SelPHosting Configuration Management Core [EB/ OL]. (2008 - 04) [2011 - 04,]. http ://www. xilin, com/sup- port/documentation/application_notes/xapp989, pdf.
  • 10Carmichael C, Chen W T. Correcting Single-event Upsets in Virtex-4 FPGA Configuration Memory[R]. Xilinx Applica- tion Note XAPP1088, 2009.

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部