IEEE1588时钟同步系统应用分析与现场测试

Application analysis and field test of IEEE 1588 clock synchronization system

介绍了数字化变电站IEEE1588同步对时系统的结构及特点,重点分析了不同模式情况下的实现机制与差别,提出了合并单元同步性能、主备时钟切换性能等项目的测试方法,通过实际工程测试得出了2个合并单元输出的采样值角差的变化以及主备时钟切换各环节延时等数据。最后结合测试中遇到的问题,提出了过程层网络主备时钟切换试验的重要性,并给出了对于合并单元的一些建议。

The structure and feature of IEEE 1588 clock synchronization system for digital substation are introduced,and its implementation mechanisms under different modes are emphatically analyzed.The methods for testing the performance of merging unit synchronization and master-standby clock changeover are proposed.The sampling angle difference between two merging units and the delay of each section during master-standby clock changeover are measured by engineering test.The importance of master-standby clock changeover test at process layer network is stressed and some suggestions for the merging unit are proposed.