基于DLL的低功耗时钟分布策略

DLL-Based Low Power Clock Distribution Scheme

时钟树综合对于现代数字电路设计必不可少。但目前时钟树综合方案级数过深，功耗过大。针对此问题，提出了一种新的基于DLL的去偏斜电路放宽了时钟树综合偏斜约束，并降低了时钟树功耗。在0．13um工艺下实现了测试芯片。测试结果表明初始偏斜在lOOps时，此方案可以使偏斜减小44％。此电路放宽了对时钟树综合的约束。通过使用该电路，时钟树功耗从1w减小到700roW，降低了30％。

Clock tree synthesis is essential for modern digital circuits. Current CTS flow need a high-depth clock tree, while consuming more power. A novel DLL-based deskew circuit is proposed, to relax clock synthesis constraint and minimize the power consumption of the clock tree. A test chip is implemented under 0.13urn process. The measurement has proved the skew could decrease by 44% When initial skew is 100ps. This circuit could decrease power of clock tree from 1W to 700mW, by 30%.