摘要
This paper designs a binary-weighted programmable gain amplifier（PGA） with a DC offset cancellation （DCOC） circuit and an AB-class output buffer.The PGA adopts the circuit topology of a differential amplifier with diode-connected loads.Simulation shows that the performance of the PGA is not sensitive to temperature and process variation.According to test results,controlled by a digital signal of six bits,the PGA can realize a dynamic gain of-2 to 61 dB,and a gain step of 1 dB with a step error within±0.38 dB.The minimum 3 dB bandwidth is 92 MHz.At low-gain mode,IIP3 is 17 dBm,and a 1 dB compression point can reach 5.7 dBm.The DCOC circuit enables the amplifier to be used in a direct-conversion receiver and the AB-class output buffer circuit reduces the overall static power consumption.
This paper designs a binary-weighted programmable gain amplifier（PGA） with a DC offset cancellation （DCOC） circuit and an AB-class output buffer.The PGA adopts the circuit topology of a differential amplifier with diode-connected loads.Simulation shows that the performance of the PGA is not sensitive to temperature and process variation.According to test results,controlled by a digital signal of six bits,the PGA can realize a dynamic gain of-2 to 61 dB,and a gain step of 1 dB with a step error within±0.38 dB.The minimum 3 dB bandwidth is 92 MHz.At low-gain mode,IIP3 is 17 dBm,and a 1 dB compression point can reach 5.7 dBm.The DCOC circuit enables the amplifier to be used in a direct-conversion receiver and the AB-class output buffer circuit reduces the overall static power consumption.
基金
supported by the National Found for Fostering Talents of Basic Science,China(No.J0730318)
the National Science and Technology Maior Project,China(Nos.J2009ZX03007-001-03,2010ZX03007-002-03)
