基于预缓冲机制的低功耗指令Cache

Low-power Instruction Cache Based on Predict Buffer Mechanism

为降低微处理器中片上Cache的能耗,设计一种基于预缓冲机制的指令Cache。通过预缓冲控制部件的预测,使处理器需要的指令尽可能在缓冲区命中,从而避免访问指令Cache所造成的功耗。对7个测试程序的仿真结果表明,预缓冲机制能节省23.23%的处理器功耗,程序执行性能平均提升7.53%。

This paper designs an instruction Cache based on Predict Buffer（PB） mechanism to reduce the energy consumption of on-chip Cache of the processor.It can make instruction needed by processor hit in buffer mostly by PB control component predict,thus power dissipation of instruction Cache can be avoided.Simulation result of seven benchmarks shows that PB mechanism can save more than 23.23% power and improve performance by 7.53%.