基于优化编码的LFSR重播种测试压缩方案

A Test Compression Scheme Based on LFSR Reseeding and Optimized Coding

大规模高密度集成电路测试中存在测试数据量大、测试功耗高等问题.提出了一种先通过编码优化测试集,再使用线性反馈移位寄存器(linear feedback shift register,LFSR)重播种的内建自测试方案.该方案通过自动测试模式生成工具得到被测电路的确定测试集,再压缩为种子集存储在片上ROM中.压缩测试集的过程中,首先以降低测试功耗为目标,用少量确定位编码测试集中的部分测试立方,来增强解码后测试模式相邻位之间的一致性;然后以提高压缩率同时降低LFSR级数为目标,将测试立方编码为确定位含量更少的分段相容码(CBC),最后将以CBC编码的测试立方集压缩为LFSR种子集.实验证明所提出的方案在不影响故障覆盖率的前提下大量降低了测试功耗,并且具有更高的测试数据压缩率.

The high density and large-scale IC meets lots of problems during testing, such as huge amount of test data, excessive test power dissipation and so on. This paper presents a scheme of test data compression, which optimizes a set of deterministic test cubes by encoding approach before using linear feedback shift register （LFSR） reseeding. The deterministic t^est set is obtained by using an automatic test pattern generation （ATPG） software. The test set is compressed to a seed set and stored in ROM on the chip. In the process of compression, firstly, a few specified bits are used to encode partial test cubes for enhancing the consistency between adjacent bits of the cube. This process is aimed at reducing test power. Secondly, in order to improve the encoding efficiency of test compression and even further reduce test storage, the test cubes are encoded to new test cubes by compatible block code （CBC）. Finally, the new test cubes are compressed to LFSR seeds. The specified bits in test set encoded with CBC are much less than the original deterministic test set, so the number of stages in LFSR is reduced. Experimental results on ISCAS-89 benchmark show that the scheme can not only reduce test power but also increase the encoding efficiency.