期刊文献+

基于FPGA的16位堆栈处理器的设计 被引量:3

Design of FPGA-based 16-bit Stack Processor
下载PDF
导出
摘要 设计了一款面向嵌入式控制领域的16位堆栈处理器,该处理器包含两个堆栈:执行数学表达式的数据堆栈和支持子程序调用的返回堆栈,其指令集含35条堆栈指令.详细给出了该堆栈处理器的体系结构及设计方法;不仅采用简单有效的指令编码方式缩小了代码体积,同时给出了单周期操作多个堆栈元素的解决方法.该处理器采用FPGA实现,在XC5VLX110T芯片上的运行时钟频率最高达到146.7MHz.最后给出了设计的软件仿真与硬件综合结果. This paper introduces a 16-bit stack processor for embedded control.The stack processor has two stacks: a data stack for evaluating mathematical expression and a return stack for calling subroutine.The instruction set includes 35 stack instructions.The architecture and design of the stack processor are presented.Not only a simple and effective instruction encoding is adopted to reduce the code size,but also the method to operate multiple stack elements in a single cycle is proposed.The processor is implemented by FPGA.Finally,the results of software simulation and hardware synthesizing are presented,and it comes out that the processor is able to run up to 146.7MHz on XC5VLX110T.
出处 《微电子学与计算机》 CSCD 北大核心 2012年第2期22-26,共5页 Microelectronics & Computer
基金 南京航空航天大学引进人才科研启动基金(S1028-042)
关键词 堆栈处理器 嵌入式 FPGA Stack Processor Embedded FPGA
  • 相关文献

参考文献8

  • 1Leo Brodie. Thinking forth [M]. USA: Punchy PUB, 2004: 25-26.
  • 2Shi H, Bailey C. Investigating available instruction level parallelism for stack based machine architectures [C]ffProceedings of Euromiero Symposium on Digital Systems Design. Rennes, France, 2004: 112-120.
  • 3李楠,喻明艳.16×16快速乘法器的设计与实现[J].微电子学与计算机,2008,25(4):156-159. 被引量:8
  • 4宣淑巍,李晓江,马成炎.一种基于循环减法原理除法器的加速方法[J].微电子学与计算机,2009,26(12):12-15. 被引量:7
  • 5Richard E Haskell. A VHDL-Forth core for FPGAs [J]. Microprocessors and Mierosystems, 2004, 28 (3) :115-125.
  • 6Bernd Paysan. bl6-A forth processor in an FPGA [EB/OL]. [2010-07-20]. http.//www, jwdt. com/~ paysan/bl6, html.
  • 7James Bowman. The J1 forth CPU [EB/OL]. [2010- 07-21]. http://excamera, com/sphinx/fpga-jl, html.
  • 8Leong P H W, Tsang P K, Lee T K. A FPGA based Forth microprocessor[C]//Proceedings of IEEE Sym- posium on FPGAs for Custom Computing Machines. Napa Valley, California, 1998: 254-255.

二级参考文献10

共引文献13

同被引文献22

  • 1刘乔寿,张毅.SPCE061A与IDE硬盘之间的数据接口[J].信息技术,2005,29(12):51-53. 被引量:1
  • 2Fraser C W, Hanson D R. A retargetable C compiler: designand implementation [ M ]. [ s. 1. ] : Benjamin/Cu - turnings Pub. Co. , 1995.
  • 3Fraser CW,Hanson DR.可变目标C编译器-设计与实现[M].王挺,黄春译.北京:电子工业出版社,2005.
  • 4Pelegri- Llopart E. Rewrite Systems, Pattern Matching, and Code Generation [ D ]. Berkeley: University of California, 1987.
  • 5Pelegri-Llopart E,Graham S L. Optimal code generation for expression trees: An application of BURS theory [ C ]//Pro- ceedings of the 15th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages. New York :ACM, 1988 : 294-308.
  • 6Fraser C W,Henry R R,Proebsting T A. BURG-Fast Optimal Instruction Selection and Tree Parsing[ J ]. SIGPLAN Notices, 1992,27 (4) :68-76.
  • 7Fraser C W,Hanson D R. The lcc 4. x code-generation inter- face[ R]. Redmond ,WA: [ s. n. ] ,2001.
  • 8Koopman P J. Stack computers: The new wave [ M ]. Califor- nia:Ed. Mountain View Press,1989.
  • 9Phil Koopman. Stack Computers: the new wave [M]. New York: Chichester: E. Horwood, 1989: 59-60.
  • 10Richard E Haskell. A VHDL--Forth Core for FPGAs [J]. Microprocessors and Microsystems, 2004, 28 (3) :115-125.

引证文献3

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部