异步FIFO控制器的设计

Asynchronous FIFO controller design

异步FIFO是一种先进先出电路,可以有效解决异步时钟之间的数据传递。通过分析异步FIFO设计中的难点,以降低电路中亚稳态出现的概率为主要目的,提出了一种格雷码计数器的技术,通过仿真验证,有效地实现了异步FIFO控制器的设计。该设计将大大提高工作频率和资源利用率。

Asynchronous FIFO is a first-in-first out circuit, which can effectively transmit data among asynchronous clocks. This paper analyses the difficult points of asynchronous FIFO design. In order to reduce the probability of metastability in the cir- cuit, the paper presents the technique of gray code counter. Through simulations validate, effective achieved the design of asyn- chronous FIFO controller. This design improves the frequency of workings and the utilization of resources greatly.