摘要
IEEE802.16e标准定义的准循环低密度奇偶校验(LDPC)码是一种线性分组码。针对LDPC码校验矩阵的稀疏准循环特性,对基于部分并行结构的归一化最小和(NMS)译码算法进行了研究,给出了译码信息量化和信息交换的方法。通过数值仿真验证了译码算法在高斯信道中的译码性能,并利用现场可编程门阵列(FPGA)对该译码算法进行了实现。
The quasi-cyclic low density parity check codes（LDPC） defined in IEEE802.16e standard is a kind of nonlinear block codes.A normalized min-sum（NMS） algorithm based on partly parallel structure is studied aiming at the sparse and quasi-cyclic characteristics of parity-check matrix of LDPC codes.The methods for quantizing and exchanging the decoding messages are given.The Performance of decoding algorithm in Gaussian channel is verified by numerical simulation.The decoding algorithm is implemented by Field Programmable Gate Arrays（FPGA）.
出处
《无线电工程》
2012年第2期55-57,64,共4页
Radio Engineering
关键词
纠错码
低密度奇偶校验码
归一化最小和算法
准循环
error-correction codes
low-density parity-check codes
normalized min-sum algorithm
quasi-cyclic
