一种高速低功耗存储读写控制电路

A High-Speed Low-Power Memory Read-and-Write Control Circuit

本文提出了一种高速低功耗存储读写控制电路。该电路采用锁存器型敏感放大器,并将敏感放大器输入与存储器位线通过隔离电路互联,通过控制隔离电路和敏感放大器开启时机,可以有效实现存储器读出速度、读数据功耗和读出可靠性之间的折衷。文章给出的模拟分析结果对存储器设计者有很好的参考价值。

A high-speed low-power memory read-and-write control circuit is analyzed. In the circuit a latch-based sense amplifier is used and the input of the amplifier is connected to the bit lines of the memory through isolation transistors. Trade-off can be made between the read delay, power dissipation and read reliability of a memory by controlling the timing of the isolation transistor and the sense amplifier. The simulation results in this paper will be useful for memory designer.