助听器多通道宽动态范围压缩的低功耗硬件实现

Low power hardware implementation of multi-channel wide dynamic range compression for digital hearing aids

多通道宽动态范围压缩(WDRC)是数字助听器听力补偿的常用算法,其增益计算涉及较多非线性运算(对数、指数),硬件实现功耗较大.为解决该问题,根据增益计算中声压级(SPL)检测的特点,提出一种基于查表法的多通道WDRC低功耗硬件实现方法,将信号的平均能量直接映射为线性刻度的增益,完全避免了非线性运算.并且,该方法采用合适的表格区间划分达到较小的误差;对查表结果进行递归平滑,抑制增益波动的同时,可灵活调整启动时间和释放时间.仿真表明,该方法得到的增益与直接计算的结果比较吻合,且波动较小.此外,因无需对I/O曲线作分段线性的约束,使该方法具有较大的配置灵活性.在SMIC的0.13μm工艺条件下,基于该方法完成了32通道WDRC的VLSI设计并流片.实测结果表明,该设计的功耗仅为19.2μW.

The multi-channel wide dynamic range compression（WDRC） algorithm,which involves many non-linear operations（logarithm and exponent） and is highly power-consuming,is commonly used in digital hearing aids.According to the characteristics of the sound pressure level（SPL） detection in WDRC gain computing,a low power hardware implementation method for multi-channel WDRC based on a lookup table was proposed in this paper.In this method,the input signal＇s mean power was directly mapped to the WDRC gain without non-linear operations.The method only introduced small errors by using proper power interval division,inhibiting the fluctuations of the gains through a recursive smoothing operation on the results of the lookup table,while at the same time easily adjusting the attack time and release time.The simulation result shows that the gains obtained by the proposed method are consistent with the computing result with smaller fluctuations.Furthermore,because of no piece-wise linear constraint for the I/O curves,the method has greater configuration flexibility.The VLSI design of a 32 channel WDRC module based on the proposed method was realized in the SMIC 0.13 μm process.The test result shows that the power dissipation of the design is only 19.2 μW.