65nm工艺下百万门级芯片的物理设计

Physical design of a million-gate chip with 65nm process technology

随着集成电路工艺的发展,集成电路后端物理设计变得越来越复杂,遇到了很多新的挑战。本文介绍了一款65nm工艺百万门级芯片的物理设计过程,论述了在布局规划、电源网络规划、时钟树设计、信号完整性、可制造性设计等方面的解决方案,提出了设计方法学上的改进,提高了后端物理设计效率和芯片的良率。

With the development of integrated circuit process technology,the IC physical design becomes tremendously complex and encouters many challenges that never arise before. This paper presents a physical design implementation for a million-gate chip using 65nm technology node. Detailed discussion includes the methods for resolving new issues of floorplan, power plan, clock tree design, signal integrity and design for manufacturing. With these design methods, the physical design efficiency and chip yield can be greatly improved.