并行片上网络仿真器ParaNSim的设计及性能分析

ParaNSim: a Parallel Network-on-Chip Simulator

为了减少使用仿真器对片上网络的性能、结构等进行仿真的时间,提高仿真效率,利用当代计算机的并行计算能力,设计并实现了一个并行片上网络仿真器ParaNSim.该仿真器可配置拓扑、路由算法以及虚通道等参数,既可以作为独立的仿真器使用,也可以作为一个子模块嵌入其他仿真器(如Multi2Sim)中;经过实验验证,其并行仿真能达到的加速比平均约为210%,最大加速比可达250%,因此它能有效地减少仿真时间,为大规模片上网络的仿真提供支持.

It is a very popular approach to use simulators to evaluate the performance and cost of different network-on-chips（NOCs） for determining the best network designs and configurations.Most of the traditional simulators are of single thread,which is a computational bottleneck of these simulators because single thread renders them cannot take advantages of new chip multiprocessors.A parallel NOC simulator,ParaNSim,is designed and implemented in this paper.The simulator supports large-scale NOC simulation,and can effectively reduce the simulation time for large-scale NOC simulation.Experimental result shows that the speedup of parallel simulation can reach 210% on average,and 250% the maximum.