基于FPGA的不可分层LDPC码译码器

Layered Decoder Design for Non-layered LDPC Codes Based on FPGA

针对不可分层LDPC码无法采用分层译码算法的问题,设计了一种新型的LDPC码分层译码器。与传统分层译码器的结构不同,新结构在各层间进行并行更新,各层内进行串行更新。通过保证在不同分层的同一变量节点不同时进行更新,达到分层译码算法分层递进更新的目标。选用Altera公司的CycloneⅢ系列EP3C120器件,实现码率3/4,码长8 192的(3,12)规则不可分层QC-LDPC码译码器的布局布线,在最大迭代次数为5次时,最高时钟频率可以达到45.44 MHz,吞吐量可以达到47.6 Mbps。

As layered-decoding algorithm can not be used by non-layered LDPC codes, a new architecture for layered-decoding algorithm is proposed in this paper. Different from traditional architecture, the new design uses parallel updating among layers and serial updating within each layer. With the same variable nod updated at different time in different layers, message for every variable can be updated layer by layer. The design can complete decoding for 3/4 code rate,8 192 code length, （ 3,12 ） regular non-layered QC-LDPC codes. The whole design is synthesized under Cyclone Ⅲ EP3C120 FPGA of Altera, Inc. After routed, the highest clock frequency can reach 45.44 MHz. When the maximum iteration number is set to 5,the decoder throughput can reach 47.6 Mbps.