90 nm CMOS全数字锁相环设计与实现

Design and Implementation of ADPLL Based on 90 nm CMOS Process

设计了一种基于90nm CMOS工艺的全数字锁相环,重点介绍了几种子模块电路结构,包括鉴频鉴相器、时间数字转换器、数字控制振荡器和新型2阶数字滤波器,分别对其性能进行了分析。仿真测试结果表明,该锁相环具有输出频率高、锁定时间短、抖动小等特点。

An all-digital PLL based on 90 nm CMOS process was proposed.Several sub-module circuits of the PLL,including PFD,TDC,DCO and a novel 2nd-order digital filter,were discussed in detail,and their performances were analyzed,respectively.Simulation and test results showed that the proposed PLL had the advantages of high output-frequency,short lockout time and low jitter.