一种基于全数字锁相环的SRAM实速测试方案

An At-Speed Test Scheme for SRAM Using On-Chip ADPLL

提出了一种采用实速测试方式测试SRAM性能参数及可靠性的方案。该方案在内建自测试(BIST)电路的基础上,通过增加一个超高速ADPLL为SRAM性能的实速测试提供一个高频时钟,同时还加入延时链来产生不同相位的4个时钟。通过调整这4个时钟的相位来获得SRAM的关键性能参数,如存取时间、地址建立和保持时间等。该方案在UMC 55nm CMOS标准逻辑工艺下流片验证。测试结果显示,SRAM最大测试工作频率约为1.3GHz,测试精度为35ps。

A novel test scheme was proposed for at-speed test of SRAM performance.Based on built-in self-test（BIST） circuit,an all digital phase locked loop（ADPLL） was added to generate high frequency clock for at-speed test of SRAM performance.Delay chains were incorporated to achieve four phase clocks.By adjusting the four clocks,key parameters of SRAM,such as access time,address settling and hold times,could be obtained.Test chip was fabricated in UMC＇s 55 nm CMOS logic standard process.Test results showed that the SRAM had a maximum working frequency of around 1.3 GHz,and test accuracy reached 35 ps.