图像旋转VLSI流水结构设计

A pipelined VLSI design for image rotation

提出了一种基于3步平移算法的实时图像二维旋转VLSI流水结构.该结构采用了一种新颖的缓存机制,通过错位存储中间结果和单独存储列平移量的方式,显著减少了片上存储器的总容量,同时也减少了整个旋转过程中无效数据的处理量,提高了数据通过率.该设计采用SMIC 0.18μm CMOS工艺进行了流片,在100MHz工作频率下,对一幅512×512的图像旋转45°,处理时间约为3.81ms,满足了大多数图像处理系统的实时性要求.

A pipelined VLSI architecture for three-pass rotation algorithm was proposed, in which a buffer scheme was used. This architecture buffers the intermediate results in the dislocated order and stores the offsets in the horizontal direction separately. As a result, both the area of on-chip memory and the amount of pixels processed were reduced. The design was fabricated by SIMC （Semiconductor Manufacturing International Corporation） 0.18 μm CMOS （complementary metal oxide semiconductor） technology. Experimental results show that it only takes 3.81 ms at 100 MHz to rotate a 512 × 512 image by the angle 45°, which meets the real-time requirement for many application systems.