A novel lambda negative-resistance transistor in the 0.5 μm standard CMOS process

A novel negative-resistance transistor (NRT) with a Lambda shaped I-V characteristic is demonstrated in the 0.5 μm standard CMOS process. To save on the number of component devices, this device does not use standard device models provided by CMOS processes, but changes a MOSFET and a BJT into a single device by fabricating them in the same n-well, with a p-type base layer as the MOSFET's substrate. The NRT has a low valley current of -6.82 nA and a very high peak-to-valley current ratio of 3591. The peak current of the device is -24.49 μA which is low enough to reduce the power consumption of the deivce, and the average value of its negative resistance is about 32 kΩ. Unlike most negative-resistance devices which have been fabricated on compound semiconductor substrates in recent years, this novel NRT is based on a silicon substrate, compatible with mainstream CMOS technology. Our NRT dramatically reduces the number of devices, minimizing the area of the chip, has a low power consumption and thus a further reduction in cost.

A novel negative-resistance transistor （NRT） with a Lambda shaped I-V characteristic is demonstrated in the 0.5 μm standard CMOS process. To save on the number of component devices, this device does not use standard device models provided by CMOS processes, but changes a MOSFET and a BJT into a single device by fabricating them in the same n-well, with a p-type base layer as the MOSFET＇s substrate. The NRT has a low valley current of -6.82 nA and a very high peak-to-valley current ratio of 3591. The peak current of the device is -24.49μA which is low enough to reduce the power consumption of the deivce, and the average value of its negative resistance is about 32 kg）. Unlike most negative-resistance devices which have been fabricated on compound semiconductor substrates in recent years, this novel NRT is based on a silicon substrate, compatible with mainstream CMOS technology. Our NRT dramatically reduces the number of devices, minimizing the area of the chip, has a low power consumption and thus a further reduction in cost.