一个低功耗1G-samples/s,6-bit折叠插值ADC芯片设计

A low power 1G-samples/s,6-bit folded interpolation ADC integrated circuit design

本文提出了一种具有高线性度的折叠,插值结构数模转换器(ADC)。与高速并行数模转换器(Flash ADC)相比较,该结构具有面积小,功耗低的特点,适用于低功耗超宽带(UWB)接收机中。本文对电路各部分进行了设计,并在SMIC 0.18μm工艺下完成了版图设计和后仿真。版图核心电路面积(不包括PAD)仅为0.45mm2,在1G samples/s采样率,输入信号为488.77MHz时,总功耗仅为57mW,有效位(ENOB)达到5.74bits。

A high-linearity folded interpolation anolog-to-digital converter （ADC）is proposed, which has less area and lower power consumption than high-speed full-parallel ADC （Flash ADC）, suitable for low-power ultra-wideband （UWB） receiver. All parts of this circuit are designedl and the layout design and post simulation are performed with SMIC 0.18μm process. Layout core area （without pads） is only 0.45mm^2. The total power consumption is only 57mW at the sample rate of 1G samples/s and input signal frequency of 488.77MHz, and the effective number of bits （ENOB） achieves 5.74 bits.