AES算法中基于流水线的可逆S盒设计与实现

Design and Implementation of Pipelining Reversible S-BOX in AES Algorithm

AES中S盒是一个非线性的字节代替变换,在AES算法中占有较大的比重,也是整个AES加解密硬件实现的关键模块.分析基于费马定理的正逆S盒算法原理及特点,使用Verilog HDL设计可逆S盒电路,通过FPGA实现正逆S盒运算.电路引入可装配的流水线结构,设计一种小规模、快速的可逆S盒运算电路,既可实现正S盒运算,又可实现逆S盒运算,加速S盒运算的过程,减小AES加解密电路的规模,对AES算法的硬件实现具有实际价值.

In AES Algorithm,S-BOX is a nonlinear Substitute Bytes,larger proportion and important processing of AES.In this paper,S-box algorithm and characteristics with Fermat＇s theorem is analyzed,base on this algorithm,we de-signed a reversible S-BOX circuit in Verilog HDL,reversible S-BOX is realized by FPGA.The reversible S-BOX cir-cuit is composed of pipelining circuit,with small-scale,and high speede,it implements both S-BOX and inverse S-BOX operations for speeding up the process of reversible s-box operations,reducing the scale of AES encryption and decrypt-ion circuit,these circuits hold practical value to AES Algorithm with Hardware implementation.