基于SV语言的UART模块功能验证

Functional Verification of UART Module Based on SystemVerilog

随着半导体工艺的发展,SoC芯片的规模和复杂度日益增大,传统的验证方法已经不能满足要求。本文介绍了基于SystemVerilog验证语言的形式化验证和VMM验证这两种功能验证的方法,并且结合使用这两种方法对一个UART接口模块进行了验证,在保证验证完备性的基础上,有效地提高了功能验证的效率。

With the development of semiconductor technology, SoC chip＇s size and complexity increasing fast, the traditional verification method can not meet the requirements. This article describes two functional verification methods based on System- Verilog verification language： formal verification and VMM verification, and use a combination of these two methods for a UART interface module＇ s verification. This varification program ensures the functional verification＇ s completeness, and effec- tively improves the efficiency.