一种高速延时无关同异步转换接口电路

A High-Speed Delay-Independent Synchronous to Asynchronous Interface

针对传统片上系统设计同步时钟引起的功耗大、IP核可重用性差等缺点,提出一种可用于多核片上系统和片上网络的快速延时无关同异步转换接口电路.接口由采用门限门的环形FIFO实现,移除了同步时钟,实现了数据从同步时钟模块到异步模块的高速传输,支持多种数据传输协议并保证数据在传输中延时无关.基于0.18μm标准CMOS工艺的Spice模型,对3级环形FIFO所构成的传输接口电路进行了仿真,传输接口的延时为613ps,每响应一个传输请求的平均能耗为3.05pJ?req,可满足多核片上系统和片上网络芯片速度高、功耗低、鲁棒性强和重用性好的设计要求.

This paper proposes a novel interface used in multi-processor system-on-chip and network-on-chip.The interface,which is implemented by the circular FIFO with threshold gate,removes the synchronous clock from sender.It resolves the problems of high power consumption induced by clock signal and low reusability of IP cores.With the transmission mode combining both serial and parallel communication,data of different widths can be transferred from synchronous sender to asynchronous receiver rapidly.Since the distributed framework is utilized,the data transport channel is separated from the transfer control block,as the synchronizer and write read pointer.In this way,the different reliability of the interface can be satisfied by the interface during changing the number of synchronizer stages.And various asynchronous transport protocols are supported gracefully by the interface.While the two-rail encoding transfer manner is selected,the transmission is quasi-delay insensitive and the data integrity is ensured.Based on SMIC 0.18 μm CMOS technology,simulation results of 3 stages FIFO have shown that the delay is 613ps with the average energy consumption of 3.05pJ for one transfer request responded,which can satisfy the requirements of high speed,low power,strong robustness and good reusability in the design of multiprocessor SoC and network-on-chip.