基于低摆幅互连线的NoC功耗降低技术

Power Reducing Technology of Network-on-chip Based on the Low-swing Interconnect

在高性能的片上系统设计中,功耗已经成为制约片上网络发展的重要约束。首先用混合插入方法计算了全局芯片网络中各条路径的延时和功耗。相比起用最优中继驱动器插入方法,这种情况下互连线的延时和功耗分别降低了24.36%和11.81%。在混合插入方法的基础上进行优化后,相比起用混合插入方法,互连线功耗降低了21.75%。

In the high-performance SoC design,power consumption becomes the main design constraint of NoC.In this paper,the author computes each path’s latency and power using hybrid insertion strategy first.In this case,the latency and power of interconnect are reduced by 24.36% and 11.81% than optimized repeater insertion,respectively.After the approach being optimized,the power of global interconnects has a reduction of 21.75% compared with HI strategy.